Re: [myhdl-list] Xilinx simulation

[Edward V. <dev...@sb...>]

 Chris & Henry
I am using ISE.  I don't have Vivado since I looked at Xilinx it was around $2900.00
I did not get the Verilog simulation working, nothing I did. would make the res_out_x
signal respond to the stimulus.  It was always red and would not turn green.I did get a VHDL simulation working less the instances of m_flatten.
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/tbjp_procesvhd.vhdWhen I use m_flatten.v I get multiple errors of like the one.
Line 22: <None> is not declared.
When I use m_flatten.vhd I have to modify _flat to flat to get the instances to work
since I get multiple errors Line 37: Illegal identifier : _flat
Still don't know how to create the wrapper for m_flatten.As always any help will be greatly appreciated.
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613 


     On Tuesday, March 24, 2015 12:52 AM, Henry Gomersall <he...@ca...> wrote:
   

 On 24/03/15 01:12, Edward Vidal wrote:
> In jp_process.v res_out_x is defined as below.
> output signed [9:0] res_out_x;
> reg signed [9:0] res_out_x;
> What do you have to do make the signal respond to Xilinux stimulus?
> Currently using wire signed [9:0] res_out_x;  I have tried reg [9:0] 
> res_out_x;

It's not entirely clear to me what you're trying to do.

I have a project that can do a cosim of sorts with Vivado:
https://github.com/hgomersall/Veriutils

It is, unfortunately, currently VHDL only. It wouldn't  be a massive job 
to add the Verilog bits if you are keen (likely a few hours work) and 
I'd be enthusiastic to see them added.

Cheers,

Henry