Re: [myhdl-list] Xilinx simulation

[Henry G. <he...@ca...>]

On 24/03/15 01:12, Edward Vidal wrote:
> In jp_process.v res_out_x is defined as below.
> output signed [9:0] res_out_x;
> reg signed [9:0] res_out_x;
> What do you have to do make the signal respond to Xilinux stimulus?
> Currently using wire signed [9:0] res_out_x;  I have tried reg [9:0] 
> res_out_x;

It's not entirely clear to me what you're trying to do.

I have a project that can do a cosim of sorts with Vivado:
https://github.com/hgomersall/Veriutils

It is, unfortunately, currently VHDL only. It wouldn't  be a massive job 
to add the Verilog bits if you are keen (likely a few hours work) and 
I'd be enthusiastic to see them added.

Cheers,

Henry