Re: [myhdl-list] Xilinx simulation

[Christopher F. <chr...@gm...>]

> What do you have to do make the signal respond to Xilinux stimulus?
> Currently using wire signed [9:0] res_out_x;  I have tried reg [9:0]
> res_out_x;
> All of my other signals respond to stimulus.
> Any and all help is appreciated.

Which Xilinx tools are you using?  ISE or Vivado?

You have a couple options:  First, convert a Python
testbench that generates the stimulus.  Second, use
@heng's VCD stimulus project.

Best of my knowledge co-simulation is not possible
with isim.

Regards,
Chris