[myhdl-list] Xilinx simulation

[Edward V. <dev...@sb...>]

 Hello all,Testing some code that runs okay in "python test_bench_array_jpeg_ram.py" and generates tb.vcd.  Which I can see with "gtkwave tb.vcd".https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/test_bench_array_jpeg_ram.pyModified tbjpeg_para.v to store 144 bits in
ram_lf, ram_sa, and ram_rt instead of using combine.
ran the simulation for 10.00 usec.  The res_out_x is red.
left 26
sam   a2
right a8
Xilinux simulation uses the following files:
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.v
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/ram.v
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/ram_res.v
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/rom_flgs.v
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/tbjpeg_para.v
https://github.com/develone/jpeg-2000-test/blob/masterjpeg2k/parallel_jpeg/jpeg_para.xiseIn jp_process.v res_out_x is defined as below.output signed [9:0] res_out_x;
reg signed [9:0] res_out_x;What do you have to do make the signal respond to Xilinux stimulus?Currently using wire signed [9:0] res_out_x;  I have tried reg [9:0] res_out_x;All of my other signals respond to stimulus.Any and all help is appreciated.
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613