[myhdl-list] thanks

[Edward V. <dev...@sb...>]

Hello All,
I would like to thank, Chris Felton & Josy Boelen, for all the help they have provided me. I would also to like thank all the others that 
have posted on the MyHDL mailing list.  Each of you has provided different insights into VHDL issues.
Dave Vandenbout from Xess for his XulA2 board and his "FpgasNowWhatBook.pdf".
Each of you have helped me in getting me this far in VHDL.
A special thanks to Jan Decaluwe for writing MyHDL.
I started out with no prior Python experience and none in Hardware Definition Language.
I have programmed for many years, in assembly, forth, C, Pearl, TCL/Tk, and Java.
This by far has been the most challenging effort that I have ever undertaken.
Today I think, marks a milestone, for me. My test bench performs 16 parallel Lifting Scheme using the DWT.
The image that I started with was https://github.com/develone/jpeg-2000-test/blob/master/lena_256.png.
This was a 256 x 256 gray scale.  The test bench provided 
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/sim_pass1_2.png which is the 1st level
Jpeg 2000 using the DWT.  
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/test_bench_array_jpeg.py

Steps to run test bench

git clone gi...@gi...:develone/jpeg-2000-test.git
cd jpeg-2000-test/jpeg2k/parallel_jpeg/
cp ../../lena_256.png .
python test_bench_array_jpeg.py
Runs for almost 8 minutes on 6 core AMD running Fedora20.

This generates the sim_pass1_2.png
There is still so much todo, to be able to declare sucess. If you have any questions
I will be glad to help.
 Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613