Re: [myhdl-list] A newbie question about the sequential conversion example
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From: Christopher F. <chr...@gm...> - 2015-03-20 12:47:16
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On 3/20/2015 6:08 AM, Jeremy Herbert wrote: > Hi all, > > I'm trying to get my head around myhdl, as I am definitely a python fan and > I'd like to try and use it for verilog generation. But there is a little > too much magic going on in one of the examples for me, and I was wondering > if someone could help me out. > > I'm looking at the first example on > http://docs.myhdl.org/en/latest/manual/conversion_examples.html#conv-usage > under "A small sequential design". The first problem I have is that in the > docstring of the Inc function it references a variable "n". But n is not > present as function argument or anywhere in the code. Huh? Yes, that is an error, we will get it fixed ASAP. I believe what happened, is that the example originally did have an "n" and then it was modified. > > Next, just below it, there is the following line: > > inc_inst = toVerilog(Inc, count, enable, clock, reset, n=n) > > The keyword argument 'n' is now set as equal to the variable n, which isn't > defined and also isn't used in the Inc function. What's going on here? > Where is this n coming from? As you suspected, this is an error sorry for any confusion. The example should be stated as (remove the `n`): from myhdl import * def Inc(count, enable, clock, reset): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input """ @always_seq(clock.posedge, reset=reset) def incLogic(): if enable: count.next = count + 1 return incLogic m = 8 count = Signal(modbv(0)[m:]) enable = Signal(bool(0)) clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=True) inc_inst = Inc(count, enable, clock, reset) inc_inst = toVerilog(Inc, count, enable, clock, reset) ** ToVerilogWarning: Output port is read internally: count Regards, Chris |