[myhdl-list] A newbie question about the sequential conversion example

[Jeremy H. <jer...@gm...>]

Hi all,

I'm trying to get my head around myhdl, as I am definitely a python fan and
I'd like to try and use it for verilog generation. But there is a little
too much magic going on in one of the examples for me, and I was wondering
if someone could help me out.

I'm looking at the first example on
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#conv-usage
under "A small sequential design". The first problem I have is that in the
docstring of the Inc function it references a variable "n". But n is not
present as function argument or anywhere in the code. Huh?

Next, just below it, there is the following line:

inc_inst = toVerilog(Inc, count, enable, clock, reset, n=n)

The keyword argument 'n' is now set as equal to the variable n, which isn't
defined and also isn't used in the Inc function. What's going on here?
Where is this n coming from?

Any help would be very much appreciated!

Thanks,
Jeremy