Re: [myhdl-list] bit width questions

[Christopher F. <chr...@gm...>]

<snip>
> 2 of the signals in the test bench must be set as follows for the test
> bench to run to completion.
> W0 = 9
> res_out_x = Signal(intbv(0, min= -(2**(W0)) ,max= (2**(W0))))
> x is a temp signal used to create the 144 bit input signals.  Don't
> think this signal will ever go to the FPGA.
> x = Signal(intbv(0, min=-(2**(W0)), max=(2**(W0))))
> If these signals use, (W0-1) instead of (W0), I get overflow errors.

It all depends on the range of the values used, here you
are using [-512,512) (the actual max is 511).  If you use
(W0-1) you get have that range [-256,256), no value outside
that range can be assigned to the signal.

> Is this overflow error, because you need a bit for sign?
> How is the overflow handle when the code is put in the FPGA?

This is a verification operation, the overflow will not be
handled in the FPGA synthesis.  If you have decent coverage
with your testbench you can be reasonably confident it will
not happen in the design.

>
>
> The res_out_x is signed with the inputs being extracted from 3 144 bit
> signals and 1 80 bit signal which comes from rom_flags
> VHDL
> https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.vhd
> Verilog
> https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.v
>
> VHDL
> https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/m_flatten.vhd
> Verilog
> https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/m_flatten.v
> Currently all of the code is in the tb module.  The process uses large
> code segments that I would like to resuse  without coding in place.  Is
> there restrictions where in the file the code is for simulation?

In general no (I haven't looked over the code) you will import
the modules from the file.  It is common to group design files
(reusable components) if a file(s) and the tests in a separate
file.

Regards,
Chris