[myhdl-list] bit width questions

[Edward V. <dev...@sb...>]

Hello All,

I am running a test bench https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/test_bench_array_jpeg.py
for my jpeg-2000 application.
2 of the signals in the test bench must be set as follows for the test bench to run to completion.
W0 = 9
res_out_x = Signal(intbv(0, min= -(2**(W0)) ,max= (2**(W0))))
x is a temp signal used to create the 144 bit input signals.  Don't think this signal will ever go to the FPGA.
x = Signal(intbv(0, min=-(2**(W0)), max=(2**(W0))))
If these signals use, (W0-1) instead of (W0), I get overflow errors.
Is this overflow error, because you need a bit for sign?
How is the overflow handle when the code is put in the FPGA?
 

The res_out_x is signed with the inputs being extracted from 3 144 bit signals and 1 80 bit signal which comes from rom_flags
VHDL
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.vhd
Verilog
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.v

VHDL
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/m_flatten.vhd
Verilog
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/m_flatten.v
Currently all of the code is in the tb module.  The process uses large code segments that I would like to resuse  without coding in place.  Is there restrictions where in the file the code is for simulation?

Steps to run test bench
runs for over 7 minutes on 6 core AMD.
git clone gi...@gi...:develone/jpeg-2000-test.git
cd jpeg-2000-test/jpeg2k/parallel_jpeg/
cp ../../lena_256.png .
python test_bench_array_jpeg.py Any and all help is appreciated. 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613