Re: [myhdl-list] List Of Constants

[Christopher F. <chr...@gm...>]

On 3/17/15 1:51 PM, Josy Boelen wrote:
> Christopher Felton <chris.felton <at> gmail.com> writes:
>
>>
>> <snip>
>>>
>>> I tried that code, and although it functions, the VHDL code doesn't
> get any
>>> prettier.
>>
>> I am typically not too concerned with the "prettiness" of
>> the converted code.  I think reasonable steps should be
>> taken to make it readable but not stand in the way.
>>
>> With that said I created and issue (enhancement request)
>> for this particular item:
>> https://github.com/jandecaluwe/myhdl/issues/34
>>
>> <snip>
>
> Chris,
>
> To me the prettiness of the VHDL or Verilog code is an indication of how
> 'good' the MyHDL code was drafted/converted.

I strongly disagree, you are trading off readability
and pythonics in the MyHDL code for "prettier"
intermediate code.

A similar example to yours is a straightfoward
sum-of products

     x = [Signal(intbv(...) ...]
     b = tuple(map(int, [round(1/N*xmax) for ...]))

     @always_seq(clock.posedge, reset=reset)
  	ssum = 0
	for ii in range(N):
             c = b[ii]
	    ssum = ssum + x[ii] * c
         y.next = ssum


I wouldn't write the above any other way even though
the converted code will have the case embedded in the
process.

Regards,
Chris