Re: [myhdl-list] Tool to cosimulate VHDL in Vivado

[Henry G. <he...@ca...>]

On 12/03/15 15:46, Christopher Felton wrote:
> <snip>
>> >
>> >This email is really to see if there is interest in me packaging this up
>> >and releasing it. The code is written to be solid and it has a complete
>> >test bench.
> Yes, I think you should github it and package it
> up.
>
>> >I suspect that it can be easily modified to support Verilog, and I
>> >daresay much of the effort would be applicable to other simulators that
>> >are not VPI/VHPI compliant.
> If I understand correctly, shouldn't this package
> be language agnotstic (whatever is simulated
> externally?).  Isn't the input to the external
> simulated a collection of VCD(?) stimulus and
> capture?

Not currently, though having found out properly about VCD files today, 
perhaps that would have been a better idea*.

The implementation is a generator from a LUT with a VHDL file writer 
(essentially implementing my own synchronous signal output file). This 
makes it VHDL specific, but it would be simple to write the equivalent 
for Verilog. It's not complicated, but it does work.

I'll stick it on github so you can critique it properly. Give me an hour 
or so...

Cheers,

Henry

*It's really frustrating to find this, which I did by stumbling across 
the relevant tcl commands for Vivado - it's not like I didn't make a 
concerted effort to work out the standard way of reading/writing signals 
from a simulator. That said, I still can't work out whether there is any 
way to read from a VCD file in the simulation. The FPGA world is very 
hard to penetrate.