Re: [myhdl-list] Tool to cosimulate VHDL in Vivado

[Christopher F. <chr...@gm...>]

<snip>
>
> This email is really to see if there is interest in me packaging this up
> and releasing it. The code is written to be solid and it has a complete
> test bench.

Yes, I think you should github it and package it
up.

> I suspect that it can be easily modified to support Verilog, and I
> daresay much of the effort would be applicable to other simulators that
> are not VPI/VHPI compliant.

If I understand correctly, shouldn't this package
be language agnotstic (whatever is simulated
externally?).  Isn't the input to the external
simulated a collection of VCD(?) stimulus and
capture?


Regards,
Chris