[myhdl-list] toVHDL.numericports = False

[Josy B. <jos...@gm...>]

How experimental / final is the support to use std_logic_vectors for the 
top-level in- and out-put ports in VHDL?

I had the impression it worked OK, but I recently updated my 'local' 
production copy to the latest 0.9-dev and it now seems broken. I was 
stupid enough to once not take a safety copy, which make it hard to find 
the differences ...

Regards,

Josy