Re: [myhdl-list] Interface conversion bug in 0.9-dev?

[Christopher F. <chr...@gm...>]

On 2/15/2015 1:45 PM, SHEN Chen wrote:
<snip>

> However, the constant/variable inference is broken in t2, where A.X is
> a list, and A.X0 is a slice of an element in the list.
> t2.py converts to the following verilog code. Note the if(False) line,
> it seems that a.X0 is treated as a constant, despite the "a_X[0] <= 1"
> assignment.
>
> always @(posedge clk) begin: LOGIC_PROC
>       if (False) begin
>           b <= 1;
>       end
>       else begin
>           b <= 0;
>           a_X[0] <= 1;
>       end
> end
>
> I don't think this is correct behavior.

In this complicated "container" example (signal
inside a more complicated structure) you can
always create a local reference and it should
work/help.

I posted a work around here (also changed the
example slightly, see the second and third
module).

https://gist.github.com/cfelton/1648ad98e2bda5745ec9

Not sure if this will work in your case or not.

It will take some more investigation to determine if
this is a bug or a not supported feature, and if it
is to be a not supported, can it be detected.

>
> It took me some time before I realize there is some constant v.s.
> variable inference going on.
> I'm not sure if I understood it correctly. Is there any documentation
> on this? Thank you.

We are in the process of generating the documentation
on interfaces for 0.9 release.  The only documentation
that currently exists is the MEP (MEP107).  I don't
think it describes signal/variable/constant handling.

I will add this to the documentation being added.

Regards,
Chris