Re: [myhdl-list] Interface conversion bug in 0.9-dev?

[SHEN C. <she...@co...>]

Hi all,

I hope someone could shed some light on this conversion problem,
either fixes, workarounds or points to look at in the source code.

I've been trying to switch to 0.9 and use Interface in my new project,
and this conversion problem is the last thing holding us back.
Thank you.

regards,
shenchen


On 2015-02-16 03:45, SHEN Chen wrote:

> Hi all,
>
> I found that the conversion of shadow signal in an "interface" is 
> wrong
> if the signal is in a list.
> Consider the two programs t1 and t2 at the end of the message.
>
> I define a signal A.X, and use a slice of it A.X0 as a condition in
> proc().
> I realized that it is important to have "a.X.next = 1" in the 
> process,
> otherwise a.X (and by extension a.X0) will be regarded as constants.
>
> However, the constant/variable inference is broken in t2, where A.X 
> is
> a list, and A.X0 is a slice of an element in the list.
> t2.py converts to the following verilog code. Note the if(False) 
> line,
> it seems that a.X0 is treated as a constant, despite the "a_X[0]
> https://lists.sourceforge.net/lists/listinfo/myhdl-list