[myhdl-list] Interface conversion bug in 0.9-dev?

[SHEN C. <she...@co...>]

Hi all,

I found that the conversion of shadow signal in an "interface" is wrong 
if the signal is in a list.
Consider the two programs t1 and t2 at the end of the message.

I define a signal A.X, and use a slice of it A.X0 as a condition in 
proc().
I realized that it is important to have "a.X.next = 1" in the process, 
otherwise a.X (and by extension a.X0) will be regarded as constants.

However, the constant/variable inference is broken in t2, where A.X is 
a list, and A.X0 is a slice of an element in the list.
t2.py converts to the following verilog code. Note the if(False) line, 
it seems that a.X0 is treated as a constant, despite the "a_X[0] <= 1" 
assignment.

always @(posedge clk) begin: LOGIC_PROC
     if (False) begin
         b <= 1;
     end
     else begin
         b <= 0;
         a_X[0] <= 1;
     end
end

I don't think this is correct behavior.

It took me some time before I realize there is some constant v.s. 
variable inference going on.
I'm not sure if I understood it correctly. Is there any documentation 
on this? Thank you.

regards,
Shenchen


============================== t1.py =============================
from myhdl import *

class A(object):
     def __init__(self):
         self.X = Signal(intbv(0)[8:])
         self.X0 = self.X(0)

def logic(clk, b):
     a = A()
     @always(clk.posedge)
     def proc():
         if a.X0:
             b.next = 1
         else:
             b.next = 0
             a.X.next = 1
     return proc

clk = Signal(False)
b = Signal(intbv(0)[8:])
toVerilog(logic, clk, b)
===================================================================

============================== t2.py =============================
from myhdl import *

class A(object):
     def __init__(self):
         self.X = [Signal(intbv(0)[8:]), Signal(intbv(0)[8:])]
         self.X0 = self.X[0](0)

def logic(clk, b):
     a = A()
     @always(clk.posedge)
     def proc():
         if a.X0:
         #if a.X[0][0]:
             b.next = 1
         else:
             b.next = 0
             a.X[0].next = 1
     return proc

clk = Signal(False)
b = Signal(intbv(0)[8:])
toVerilog(logic, clk, b)
===================================================================