Re: [myhdl-list] multiple instantiations

[Josy B. <jos...@gm...>]

Edward Vidal <develone <at> sbcglobal.net> writes:

<snip>
> jp_process;JP_PROCESS_JPEG_LOGIC: process (update_s, right_s(0), 
right_s(1), ..., right_s(63), flgs_s(0), flgs_s(1), ..., flgs_s(63), 
sam_s(0), sam_s(1), ... , sam_s(63), left_s(0), left_s(1), ... , 
left_s(63)) is 
>begin    
><snip>
I had noticed this behaviour before, and it will generate a warning (at 
least in the Sigasi VHDL editor). I added this to my MyHDL code in 
_toVHDL.py:
def compressSensitivityList(senslist):
    ''' reduce spelled out list items like [**name**(0), **name**(1), 
..., **name**(n)] to just **name**'''
    r = []
    for item in senslist:
        name = item._name.split('(',1)[0]
        if not name in r:
            r.append( name ) # note that the list now contains names and 
not Signals, but we are interested in the strings ...        
    return r

class _ConvertAlwaysCombVisitor(_ConvertVisitor):

    def __init__(self, tree, blockBuf, funcBuf):
        _ConvertVisitor.__init__(self, tree, blockBuf)
        self.funcBuf = funcBuf


    def visit_FunctionDef(self, node):
        self.writeDoc(node)
        senslist = **compressSensitivityList**( self.tree.senslist )
        . . .

Your list should now be a short as:
jp_process;JP_PROCESS_JPEG_LOGIC: process (update_s, right_s, flgs_s, 
sam_s, left_s) is

Regards,
Josy