Re: [myhdl-list] multiple instantiations

[Christopher F. <chr...@gm...>]

On 2/13/2015 7:52 AM, Henry Gomersall wrote:
> I think I know the answer to this, but wanted to check.
>
> I'm creating lots of instances of the same component (with different
> signals) - 128 in all. Clearly, this will lead to a pretty unwieldy vhdl
> file if every one has it's own process block.
>
> I understand I could make this neater in raw VHDL (which I can do
> through MyHDL easily enough) with the generate keyword.
>
> Is there a way to do a tight conversion for multiple equivalent
> instances? Is this one of the targets of MEP 110
> (http://dev.myhdl.org/meps/mep-110.html)?

The design is flattened and so each instance will show up
as a process in the generated file.  And yes, if this was
perceived as an issue MEP 110 would address it, MEP 110
could be used to allow one module to be instantiated many
times in the generated V* (IIRC MEP 110 is still in
draft/proposal it hasn't been accepted?).

What is the down side of the flattening?

Regards,
Chris