[myhdl-list] traceSignals and interfaces in 0.9-dev

[SHEN C. <she...@co...>]

 

Hi all, 

I started using the "interface" feature in 0.9-dev, and
really liked it. 

However, there are some quirks when I tried dumping
vcd using traceSignals(). 

Consider the three logically identical
versions of an adder listed at the end. The saved vcd contains different
set of variables: 

version 1: 

testbench
| - clk
| - xyz.x, 
| -
xyz.y,
| - xyz.z,
+- adder/
 | - clk
 | - xyz.x 
 | - xyz.y
 | - xyz.z


version 2: 

testbench
| - clk
| - xyz.x, 
| - xyz.y,
| - xyz.z,
+-
adder/
 | - clk 

version 3: 

testbench
| - clk
+- adder/
 | - clk


The simulation results of the three versions are all correct, only
that some variables in the interface are not saved in version 2 and 3.


Unfortunately, I personally prefer to write code in the style of
version 3, and really hope it to work. 

I am looking at the source code
of traceSignals() but haven't figured out what's gone wrong yet. Any
help will be appreciated. Thanks! 

regards,
shenchen 

====== version 1
====== 

from myhdl import *

class Adder(object):
 def __init__(self):

self.x = Signal(intbv(0)[8:])
 self.y = Signal(intbv(0)[4:])
 self.z =
Signal(intbv(0)[9:])

def AdderRTL(xyz, clk):
 @always(clk.posedge)
 def
hdl():
 xyz.z.next = xyz.x + xyz.y
 return hdl

def testbench():
 clk =
Signal(False)
 xyz = Adder()

 adder = AdderRTL(xyz,clk)


@always(delay(10))
 def clkgen():
 clk.next = not clk

 @instance
 def
stimulus():
 yield clk.negedge
 xyz.x.next = 2
 xyz.y.next = 3
 yield
clk.posedge
 raise StopSimulation

 return clkgen, stimulus, adder

tb =
traceSignals(testbench)
sim =
Simulation(tb)
sim.run()

================= 

====== version 2 ======


from myhdl import *

class Adder(object):
 def __init__(self):
 self.x
= Signal(intbv(0)[8:])
 self.y = Signal(intbv(0)[4:])
 self.z =
Signal(intbv(0)[9:])

 def rtl(xyz, clk):
 @always(clk.posedge)
 def
hdl():
 xyz.z.next = xyz.x + xyz.y
 return hdl

def testbench():
 clk =
Signal(False)
 xyz = Adder()

 adder = xyz.rtl(clk)


@always(delay(10))
 def clkgen():
 clk.next = not clk

 @instance
 def
stimulus():
 yield clk.negedge
 xyz.x.next = 2
 xyz.y.next = 3
 yield
clk.posedge
 raise StopSimulation

 return clkgen, stimulus, adder

tb =
traceSignals(testbench)
sim =
Simulation(tb)
sim.run()

================= 

====== version 3 ======


from myhdl import *

class Adder(object):
 def __init__(self):
 self.x
= Signal(intbv(0)[8:])
 self.y = Signal(intbv(0)[4:])
 self.z =
Signal(intbv(0)[9:])

 def rtl(xyz, clk):
 @always(clk.posedge)
 def
hdl():
 xyz.z.next = xyz.x + xyz.y
 return hdl

def testcase1():
 def
testbench():
 clk = Signal(False)
 xyz = Adder()

 adder =
xyz.rtl(clk)

 @always(delay(10))
 def clkgen():
 clk.next = not clk


@instance
 def stimulus():
 yield clk.negedge
 xyz.x.next = 2

xyz.y.next = 3
 yield clk.posedge
 raise StopSimulation

 return clkgen,
stimulus, adder

 tb = traceSignals(testbench)
 sim = Simulation(tb)

sim.run()

testcase1()

=================