Re: [myhdl-list] myhdl.AlwaysCombError: signal (startmpy) used as inout in always_comb function argument

[Josy B. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:

> 
> <snip>
> >> I believe the inout comb detection is a mechanism to
> >> protect against unwanted comb feedback.  If you have
> >> a complicated  <at> always_comb it probably make sense to
> >> split it out rather than remove the comb feedback
> >> detection.
> >
> > What is **unwanted comb feedback**?
> 
> Combinational loops [1][2] as a result of a complicated
> expression.
> 
> > Is this in the Verilog LRM? Or is
> > the comb feedback in the code to protect us from ourselves? If it is 
not
> > against Verilog, the **comb feedback detection** should, IMHO, be
> > reworked. If Verilog has a problem with this ... you tell me.
> 
> It is not a Verilog thing and I am not 100% sure if the
> original design intent was to protect us from ourselves
> but that is my guess.  How / why should it be reworked?
> 
> >
> > Splitting my actual code in two processes would add clumsy 
workarounds,
> > making the code not any prettier.
> >
> 
> I'm not so sure about the dual-state machine driving
> same outputs.  It's interesting, it would be the
> equivalent of a single state-machine with two state
> registers, which is just another way of logically
> organizing a more complex set of states ... hmmmm
> 
> Regards,
> Chris
> 
> [1] 
> 
http://quartushelp.altera.com/13.1/mergedProjects/verify/da/comp_file_ru
les_loop.htm
> 
> [2] http://fpga-hdl.blogspot.com/2012/07/test.html

Chris,

you are a great source of knowledge (read this as praise)
[1] : Quartus will tell me when I'm (that) stupid. I have seen this 
warning once, when I made a **ring oscillator** to generate random 
numbers (based on one of their app-notes)
I posted the code for your perusal-> 
https://github.com/josyb/KalmanFilter
I've written it this way, as this is what I would have written in VHDL. 
One other example where I used this was for a DDR2 SDRAM controller 
where one state-machine handles the initialisation and the second 
handles the actual read/write/refresh operation. Of course this could be 
done in a single state machine, but this approach of divide and conquer 
generates smaller and faster code (which I can't prove right-away ...)

I think that the rework is actually removing the **check** as I showed. 
At least that is what I did locally. I'l see tomorrow how the VHDL 
synthesizes when plugged into the **real** project.

Regards,

Josy