Re: [myhdl-list] myhdl.AlwaysCombError: signal (startmpy) used as inout in always_comb function argument

[Christopher F. <chr...@gm...>]

<snip>
>> I believe the inout comb detection is a mechanism to
>> protect against unwanted comb feedback.  If you have
>> a complicated  <at> always_comb it probably make sense to
>> split it out rather than remove the comb feedback
>> detection.
>
> What is **unwanted comb feedback**?

Combinational loops [1][2] as a result of a complicated
expression.

> Is this in the Verilog LRM? Or is
> the comb feedback in the code to protect us from ourselves? If it is not
> against Verilog, the **comb feedback detection** should, IMHO, be
> reworked. If Verilog has a problem with this ... you tell me.

It is not a Verilog thing and I am not 100% sure if the
original design intent was to protect us from ourselves
but that is my guess.  How / why should it be reworked?

>
> Splitting my actual code in two processes would add clumsy workarounds,
> making the code not any prettier.
>

I'm not so sure about the dual-state machine driving
same outputs.  It's interesting, it would be the
equivalent of a single state-machine with two state
registers, which is just another way of logically
organizing a more complex set of states ... hmmmm

Regards,
Chris

[1] 
http://quartushelp.altera.com/13.1/mergedProjects/verify/da/comp_file_rules_loop.htm

[2] http://fpga-hdl.blogspot.com/2012/07/test.html