Re: [myhdl-list] myhdl.AlwaysCombError: signal (startmpy) used as inout in always_comb function argument

[Josy B. <jos...@gm...>]

Henry Gomersall <heng <at> cantab.net> writes:

> 
> On 11/02/15 15:41, Josy Boelen wrote:
> > In a module I have two state machines: one doing overall control and 
the
> > second doing a serial multiply. I (almost always) write two-process
> > state machine. As a result I have one  <at> always_comb where the 
the first
> > state machine issues a startpulse to the second and then waits for a
> > donepulse from the second to continue. Both state machine have some
> > (combinatorial or asynchronous) output signals in common so they 
have to
> > reside in the same (VHDL) process.
> <snip>
> 
> Do you have some example code?
> 
><snip>
Henry,

the code is a handful (as usual) but I made a simplified example (as 
Chris also likes to see ...):

def contrivedtwostatemachineexample( Clk, Reset,  StartP, ... )
    states_first = enum( "IDLE" , "ONE" , "TWO")
    smfp, smfn = [Signal( states_first.IDLE ) for _ in range( 2 )]
    states_second = enum( "IDLE" , "BUSY")
    smfp, smfn = [Signal( states_second .IDLE ) for _ in range( 2 )]
    startsecond, donesecond = [Signal(bool(0)) _ for _ in range(2)}
 

    @always_comb
    def smcomb():
        startsecond.next = 0
        donesecond.next = 0

        if smfp == states_first.IDLE:
            if StartP:
                smfn.next = states_first.ONE
                startsecond.next = 1
            else:
                smfn.next = states_first.IDLE

        elif smfp == states_first.ONE:
            if donesecond:
                smfn.next = states_first.TWO
                startsecond.next = 1
            else:
               smfn.next = states_first.ONE

        elif smfp == states_first.TWO:
            if donesecond:
                smfn.next = states_first.IDLE
            else:
               smfn.next = states_first.TWO


       if smsp == states_second.IDLE:
           if startsecond:
               smsn.next = states_second.BUSY
           else:
               smsn.next = states_second.IDLE
  
       elif smsp == states_second.BUSY:
           donesecond.next = 1
           # must catch an immediate start command
           if startsecond:
               smsn.next = states_second.BUSY
           else:
               smsn.next = states_second.IDLE
 
    @always_seq(Clk.posedge, reset=Reset)
    def smprocess():
        smfp.next = smfn
        smsp.next = smsn
     
   return smcomb, smprocess


You see that both **startsecond** and **donesecond** are written and 
read in the combinatorial process. MyHDL chokes on that, spitting out 
the AlwaysCombError message. But as the two signals in question are not 
**Ports** there is no real reason to do so, unless Verilog has a problem 
with it. Which is my original question: is this a problem in Verilog?

Regards,

Josy