Re: [myhdl-list] enums and non-local

[Jose M. G. C. <ch...@gm...>]

This is a piece of code that does not work. I think it is more or less equivalent to yours.


from myhdl import *

def test(clk, reset, a, b):
    t_state = enum("WAIT", "CALC")
    state = Signal(t_state.WAIT)
    @always_seq(clk.posedge, reset)
    def fsm():
        if state == t_state.WAIT:
            b.next = 0
            state.next = t_state.CALC
        elif state == t_state.CALC:
            a.next = b
            state = t_state.WAIT
    return fsm

clk = Signal(intbv(0)[1:])
reset = ResetSignal(1, active=1, async=False)
a = Signal(intbv(0)[1:])
b = Signal(intbv(0)[1:])

toVHDL(test, clk, reset, a, b)

The error is:

Local variable may be referenced before assignment: state

Thanks for your help,

	Jose M.


> El 11/2/2015, a las 14:45, Christopher Felton <chr...@gm...> escribió:
> 
> On 2/11/2015 1:11 AM, JOSE MARIA GOMEZ CAMA wrote:
>> Hello all,
>> 
>> I am trying to use an enumeration to define the states of a finite state machine. There are examples where it seems to work, but I am not able to do that. Moreover, I have gone through the code and in the _analyze.py module it seems that only intbv are allowed to be seen as non-locals. I assume there is a reason for this filtering, but there is no information. Can anyone provide a hint?
> 
> Do you have an example of the enumeration not working?  I
> have used it many times, you can peruse this example if
> you like:
> https://github.com/schoeberl/comphdl/blob/master/myhdl/vending/vending.py#L31
> 
> Also the examples on the MyHDL website:
> http://www.myhdl.org/examples/sinecomp/#design
> 
> The nonlocals are a little more complicated and will be
> enhanced (!) when porting to Py3k is completed.  In general
> using /intbv/ is the safest approach.
> 
> 
>     def m_some_module(*portmap):
> 
>         myvar = intbv(0, min=-8, max=8)
> 
>         @always...
>         def rtl():
>            myvar[:] = x + 1
>            ...
> 
> 
> Hope that helps,
> Chris
> 
> 
> 
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