[myhdl-list] myhdl.AlwaysCombError: signal (startmpy) used as inout in always_comb function argument

[Josy B. <jos...@gm...>]

In a module I have two state machines: one doing overall control and the 
second doing a serial multiply. I (almost always) write two-process 
state machine. As a result I have one @always_comb where the the first 
state machine issues a startpulse to the second and then waits for a 
donepulse from the second to continue. Both state machine have some 
(combinatorial or asynchronous) output signals in common so they have to 
reside in the same (VHDL) process.

MyHDL then complains that inouts in always_comb are not allowed.

If I comment out some code in _always_comb.py, as shown:
   def visit_Module(self, node):
#         inputs = self.inputs
#         outputs = self.outputs
        for n in node.body:
            self.visit(n)
#         for n in inputs:
#             if n in outputs:
#                 raise AlwaysCombError(_error.SignalAsInout % n)

everything goes fine, the simulation is OK and the VHDL code looks 
plausible as the 'offending' signals are well in the sensitivity list:
  KALMANFILTER_SMCOMB: process (D, smmpyp, yn, CoeffB, CoeffA, shiftc_Q, 
add_Q, mpycount, xnb, StrobeIn, shifta_Q, startmpy, mpydone, smkfp) is


The verilog conversion doesn't complain either and (as far as my Verilog 
knowledge goes) produces a plausible sensitivity list too:
  always @(D, smmpyp, yn, CoeffB, CoeffA, shiftc_Q, add_Q, mpycount, 
xnb, StrobeIn, shifta_Q, startmpy, mpydone, smkfp) begin: 
KALMANFILTER_SMCOMB

Obviously the VHDL will compile fine, I don't know about Verilog. Have I 
broken something?

Regards,

Josy