Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Christopher F. <chr...@gm...>]

<snip>
>
> and later add an always_comb function to assemble the output vector
> @always_comb
> def assignouts():
>      for i in range(Y):
>          res_out_x.next[ (i+1)*xx:i*xx] = lres_out_x[i]
>
>
> It would be nice if we can extend MyHDL to do these mappings/assignments
> with less typing.
>

This has come up in a couple threads (not this exact
topic but similar LoS/array things).  I think someone
will need to take some time and think through LoS/arrays.

We have a tricky task, we want to be able to do what the
current HDLs do but we don't want to use the current HDLs
as the benchmark :)  Meaning, we don't want to simply do
something because V* does it.  Things like multi-dimension
array/LoS could use some thought.  What is supported, what
is not, what are the limitations, is it only conversion,
etc.  When we did this exercise with interfaces we discovered
some nice tricks that you could do outside the myhdl
generators.

Regards,
Chris