Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Christopher F. <chr...@gm...>]

On 2/9/2015 10:50 AM, Edward Vidal wrote:
> Hello all,
> Thanks to Josy Boelen for getting me this far.
>
> When using arrays,  the output signal or signals, need to be created before the calling the method that creates the arrays and  @always_comb.
> How would you pass a list of signed signals? Or do they need to be signed base on the information provided by Chris Felton.?
>

Let's back up a little bit.  List of Signals (array) is
often used to represent RAM/ROM but it is also used to
logically organize signals [1][2].  If you happen to have
a very large bus you might want to break it down into
smaller logical components.  I am going to call the arrays
list-of-signals (LoS) here.

Couple things to note, LoS cannot be used as final port
interface.  In other words, you cannot convert a LoS as
a top-level port.  In a design LoS can be passed between
modules because the design is flattened.  For an actual
design it is rare that you will have a very large bus
off-chip, in the cases that you do you will need to create
mapping (like Joys example) to flatten the bus.

At this point I don't know what you are trying to achieve,
it is often difficult (i.e. takes time) to figure out your
code just from the source.  As mentioned before, simple
examples of what you are trying to achieve would help.

Here is a simple example.  I want to take a LoS (array)
of some arbitrary size and subtract some constant value
and assign it to a new LoS as the same size of the LoS
passed.

     x = [Signal(intbv(0, min=-88, max=88)
          for _ in range(N)]
     y = [Signal(intbv(0, min=-88, max=88)
          for _ in range(N)]

     def m_los_subtractor(x, y, A=7):
         N = len(x)
         @always_comb
         def rtl():
             for ii in range(N):
                 y[ii].next = x - A
         return rtl

If the above module is used in a design it should work
(disclaimer I didn't debug, there could be a typo).  An
LoS is passed that will hold the values and an LoS that
is passed will be filled with the result.  Also note,
this example is incomplete because it assumes *x* will
always be min+A.

If you are trying to convert module by module and using
LoS as ports, this will be difficult because you will have
to constantly be translating between the large flat bus
and an LoS.

I don't know if ShadowSignals are what you really want,
I would do like Joys example (I think that is what he was
doing) and map between a wide bus and an LoS and not use
ShadowSignals.

Hope this helps,
Chris

[1] 
http://docs.myhdl.org/en/latest/whatsnew/0.6.html#conversion-of-lists-of-signals
[2] 
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#ram-inference