Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Edward V. <dev...@sb...>]

Hello all,
Thanks to Josy Boelen for getting me this far.

When using arrays,  the output signal or signals, need to be created before the calling the method that creates the arrays and  @always_comb.
How would you pass a list of signed signals? Or do they need to be signed base on the information provided by Chris Felton.?

My code  is located at

https://github.com/develone/jpeg-2000-test/tree/master/jpeg2k/parallel_jpeg

array_jpeg.py, jpeg_constants.py, jp_process.v, and jp_process.vhd.
These 4 arrays are going to be on the order of 8192 bits wide for 3 arrays and 1 of 5120 bits wide. 

What method would you recommend for setting the values of these arrays 4 ram or 4 fifo instances?  

How do you determine which takes more resources?
Thanks, I do appreciate all the help.
  


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613


On Sunday, February 8, 2015 2:12 PM, Josy Boelen <jos...@gm...> wrote:
 


Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello Josy,
> 
> I thought that items on left were outputs and items on the right were 
inputs.  I was trying to follow an example  posted  Raman Muthukishnan.
> 
> I just wanted signals that  were arrays.   Since these are, I assuming 
shadow signals that is why I am not getting any output.  This is a new 
topic
 for me and I have not worked with shadow signals before.  What 
must I do to get the res_out_x or res_out_x_i to be and output?   This 
must be a really bad question.  I do appreciate all the help.
> 
> <snip>

Edward,

I think that most of your intentions, arrays and shadow signals worked 
OK. 
You have to specifically name  the output signals in the function 
declaration:
  def jp_process(sig_in_x_i, left_s_i, sam_s_i, right_s_i,flgs_s_i, 
*res_out_x*, W0=3, LVL0=4, W1=3, LVL1=4, W2=3, LVL2=4,  W3=3, LVL3=4 ):

and declare *res_out_x* before calling the function. I did remove the 
unused input signal *res_out_x_i*.

Now you are 'slicing' 1D input vectors into 1D*1D vectors (which works 
fine, it seems). So if the res_out_x is also a 1D vector, you still have 
to declare an internal 1D*1D signal and concatenate this one to a 1D 
output vector. Something like:
lres_out_x = [Signal(intbv()[xx:]) for _ in range(Y)]

and later add an always_comb function to assemble the output vector
@always_comb
def assignouts():
    for i in range(Y):
        res_out_x.next[ (i+1)*xx:i*xx] = lres_out_x[i]


It would be nice if we can extend MyHDL to do these mappings/assignments 
with less typing. 

Re-using the *res_out_x_i* as an output would be a possibility, but will 
the become an 'inout' signals, which is a very bad idea (except for the 
truly bidirectional top-level pins of the FPGA)

Regards,

JOsy
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