Re: [myhdl-list] delays in VHDL conversion

[Josy B. <jos...@gm...>]

Henry Gomersall <heng <at> cantab.net> writes:

> 
> I'm trying to do a poor man's RTL co-simulation by creating the files 
> needed for simulation and the relevant stimulus files (from the MyHDL 
> simulation), then writing the outputs from the Xilinx simulation to 
file 
> for post-simulation comparison. For this I need a clock.
> 
> Consider:
> 
> def ClkDriver(clk, period=20):
> 
>      lowTime = int(period/2)
>      highTime = period - lowTime
> 
>       <at> instance
>      def driveClk():
>          while True:
>              yield delay(lowTime)
>              clk.next = 1
>              yield delay(highTime)
>              clk.next = 0
> 
>      return driveClk
> 
> This is converted to the following (pertinent) VHDL:
> 
> architecture MyHDL of ClkDriver is
> 
> constant lowTime: integer := 10;
> constant highTime: integer := 10;
> 
> begin
> 
> CLKDRIVER_DRIVECLK: process is
> begin
>      while True loop
>          wait for lowTime ns;
>          clk <= '1';
>          wait for highTime ns;
>          clk <= '0';
>      end loop;
>      wait;
> end process CLKDRIVER_DRIVECLK;
> 
> end architecture MyHDL;
> 
> Xilinx Vivado complains this is a syntax error. It doesn't like the 
use 
> of a constant in the "wait for lowTime ns", though it's easily fixed 
> with e.g. "wait for 10 ns".
> 
> Is this Vivado being crap, or is this expected behaviour? I could 
always 
> create my own custom VHDL template, but it would be neater to have 
MyHDL 
> do it for me.
> 
> <snip>

Actually the converted code is wrong, the statements like:
    constant lowTime: integer := 10;
    wait for lowTime ns;

are incorrect, they should either be:
    constant lowTime: integer := 10;
    wait for lowTime * 1.0 ns;

or:
    constant lowTime: time := 10.0 ns;
    wait for lowTime ;

Should be easy to fix in the MyHDL code.

Regards,

Josy