Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Edward V. <dev...@sb...>]

Hello Josy,
I thought that items on left were outputs and items on the right were inputs.  I was trying to follow an example  posted  Raman Muthukishnan.
I just wanted signals that  were arrays.   Since these are, I assuming shadow signals that is why I am not getting any output.  This is a new topic for me and I have not worked with shadow signals before.  What must I do to get the res_out_x or res_out_x_i to be and output?   This must be a really bad question.  I do appreciate all the help.


Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613


On Sunday, February 8, 2015 7:44 AM, Josy Boelen <jos...@gm...> wrote:
 


Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello All,I am using the following python code to generate my Verilog 
and VHDL fileshttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/array_jpeg.pyThe files get created 
which are the following two fileshttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/jp_process.vhdand 
https://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/jp_process.vThe V
>  HDL file when I try to synthesize I get the error"Use <= to assign to 
signal res_out_x".  Changing the 4 lines where ":=:" appears to
>  "<="res_out_x((LVL0 - 1)) := (sam_s((LVL0 - 1)) - 
(shift_right(left_s((LVL0 - 1)), 1) + shift_right(right_s((LVL0 - 1)), 
1)));Process "Synthesize - XST" completed successfullyMentity jp_process 
is    port (        sig_in_x_i: in unsigned(15 downto 0);        
res_out_x_i: in unsigned(15 downto 0);        left_s_i: in unsigned(15 
downto 0);        sam_s_i: in unsigned(15 downto 0);        right_s_i: 
in unsigned(15 downto 0);        flgs_s_i:
>  in unsigned(9 downto 0)    );end entity jp_process;The Verilog file 
has no problem with the Synthesize.  I generated a Test 
Bedhttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/TBjp_process.vI am not able to see 
get the output signalhttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/nooutput.GIFAny and all help is 
appreciated.Thanks
>  <snip>
>My entity are all inputs. How do you access the output?

What'd you expect? If you don't declare outputs, you just don't have 
any. MyHDL gets mixed up between variables and signals, but I wouldn't 
blame MyHDL for that. That the Verilog converted code synthesizes is 
just a fluke (I guess to do with blocking and non-blocking?). If you let 
ISE go all the way, you very probably end up with  everything optimised 
away.
Our BDFL would say, simulate first then convert ... After all, one of 
the greatest features of MyHDL is in Simulation

Regards,

Josy



------------------------------------------------------------------------------
Dive into the World of Parallel Programming. The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net/
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list