[myhdl-list] All inputs no output with generated Verilog and VHDL

[Edward V. <dev...@sb...>]

Hello All,

I am using the following python code to generate my Verilog and VHDL files
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/array_jpeg.py
The files get created which are the following two files
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.vhd
and https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.v

The VHDL file when I try to synthesize I get the error
"Use <= to assign to signal res_out_x".  Changing the 4 lines where ":=:" appears to "<="
res_out_x((LVL0 - 1)) := (sam_s((LVL0 - 1)) - (shift_right(left_s((LVL0 - 1)), 1) + shift_right(right_s((LVL0 - 1)), 1)));
Process "Synthesize - XST" completed successfully
My entity are all inputs. How do you access the output?
entity jp_process is
    port (
        sig_in_x_i: in unsigned(15 downto 0);
        res_out_x_i: in unsigned(15 downto 0);
        left_s_i: in unsigned(15 downto 0);
        sam_s_i: in unsigned(15 downto 0);
        right_s_i: in unsigned(15 downto 0);
        flgs_s_i: in unsigned(9 downto 0)
    );
end entity jp_process;

The Verilog file has no problem with the Synthesize.  I generated a Test Bed
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/TBjp_process.v
I am not able to see get the output signal
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/nooutput.GIF
Any and all help is appreciated.
Thanks


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613