[myhdl-list] shadow signal signals signed instead of unsigned

[Edward V. <dev...@sb...>]

    

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shadow signals signed instead of unsigned
me
To
myh...@li...
Today at 7:26 AM
Hello all,
As Raman posted
Thank you very much for MyHDL. I do not know where I would be in my learning process of VHDL without MyHDL.

After seeing the posting by Raman Muthukishnan
 On shadow signals how would you modify the code to have an array of signed signals rather than unsigned.
For signed I normally use
This format res15_s = Signal(intbv(0, min = -JPEG_DATA_WIDTH, max = JPEG_DATA_WIDTH)).
This is the example posted by Raman below

from myhdl import *
def iso_pricing_check(ask_price_levels_i,price_o,WIDTH=24,NUM_LEVELS=4):
  # this line of code of slicing the signal and generating list of shadow signals is
  # not getting translated into verilog.
  ask_price_levels = [ask_price_levels_i((i+1)*WIDTH, i*WIDTH) for i in range(0, NUM_LEVELS)]
  @always_comb
  def ask_price_logic():
    # just giving the last level price as output
    price_o = ask_price_levels[NUM_LEVELS-1]
  return instances()
def convert():
    WIDTH = 32
    NUM_LEVELS = 16
    ask_price_levels_i = Signal(intbv(0)[NUM_LEVELS*24:])
    price_o = Signal(intbv(0)[WIDTH:])
    dut = toVHDL(iso_pricing_check,ask_price_levels_i,price_o,
               WIDTH=WIDTH,NUM_LEVELS=NUM_LEVELS)
convert()
I appreciate any and all help.

 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613