Re: [myhdl-list] assert and synthesizable code

[Henry G. <he...@ca...>]

On 03/02/15 20:40, Christopher Felton wrote:
> On 1/29/2015 11:38 AM, Henry Gomersall wrote:
>> >Not being terribly au fait with what is and is not synthesizable Verilog
>> >or VHDL, are python asserts converted into something that is
>> >synthesizable (or at least, will pass through the synthesis stage)?
>> >
>> >Is the better way to put the assert in a `if __debug__:` clause if I
>> >don't want it synthesized?
>> >
> Asserts with convert to something that is ignored
> by most synthesis tools.  I forget are you mainly
> targeting Verilog or VHDL?

Good question! Mainly VHDL, but with Verilog as a bonus :)

Henry