Re: [myhdl-list] Shadow signal

[Raman M. <rmu...@ho...>]

Hi Chris,
Thank you for your email.
This is the line of code that is not getting translated.     ask_price_levels = [ask_price_levels_i((i+1)*WIDTH, i*WIDTH) for i in range(0, NUM_LEVELS)]
What I am trying to achieve here is to split the 96-bit input bus  into four 24-bit signals.
In verilog we can see the declaration,  "wire ask_price_levels [0:4-1];", but there is no assignment to it.I was expecting  assignments like:   assign ask_price_levels[0] = ask_price_levels_i[23:0]   assign ask_price_levels[1] = ask_price_levels_i[46:23]

I did not write a test case for it as I was checking if I can write in such a way to split the input bus.
Thank you,Raman

> To: myh...@li...
> From: chr...@gm...
> Date: Tue, 3 Feb 2015 14:49:41 -0600
> Subject: Re: [myhdl-list] Shadow signal
> 
> On 1/27/2015 1:13 PM, Raman Muthukrishnan wrote:
> > Hi All,
> >
> > Thank you very much for MyHDL. We have been able to use it successfully for our projects.
> > I am facing one issue, and here my understanding is weak.The line of code that  creates a list of shadow signals from the input bus is not getting translated to verilog.I do not know what I am doing wrong or am missing. If you have any suggestion, it will be very helpful for me.
> 
> I don't think I understand your question or the
> code example doesn't demonstrate the error.
> 
> With 0.9dev the code appears to convert to what
> is described?  Does your testbench indicate the
> module works?
> 
> Regards,
> Chris
> 
> ~~~[Example converted code for the example]~~~
> module iso_pricing_check (
>      ask_price_levels_i,
>      price_o
> );
> 
> 
> input [95:0] ask_price_levels_i;
> output [23:0] price_o;
> wire [23:0] price_o;
> 
> 
> wire [23:0] ask_price_levels [0:4-1];
> 
> 
> 
> 
> 
> assign price_o = ask_price_levels[(4 - 1)];
> 
> endmodule
> 
> 
> 
> 
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