Re: [myhdl-list] Shadow signal

[Christopher F. <chr...@gm...>]

On 1/27/2015 1:13 PM, Raman Muthukrishnan wrote:
> Hi All,
>
> Thank you very much for MyHDL. We have been able to use it successfully for our projects.
> I am facing one issue, and here my understanding is weak.The line of code that  creates a list of shadow signals from the input bus is not getting translated to verilog.I do not know what I am doing wrong or am missing. If you have any suggestion, it will be very helpful for me.

I don't think I understand your question or the
code example doesn't demonstrate the error.

With 0.9dev the code appears to convert to what
is described?  Does your testbench indicate the
module works?

Regards,
Chris

~~~[Example converted code for the example]~~~
module iso_pricing_check (
     ask_price_levels_i,
     price_o
);


input [95:0] ask_price_levels_i;
output [23:0] price_o;
wire [23:0] price_o;


wire [23:0] ask_price_levels [0:4-1];





assign price_o = ask_price_levels[(4 - 1)];

endmodule