Re: [myhdl-list] assert and synthesizable code

[Christopher F. <chr...@gm...>]

On 1/29/2015 11:38 AM, Henry Gomersall wrote:
> Not being terribly au fait with what is and is not synthesizable Verilog
> or VHDL, are python asserts converted into something that is
> synthesizable (or at least, will pass through the synthesis stage)?
>
> Is the better way to put the assert in a `if __debug__:` clause if I
> don't want it synthesized?
>

Asserts with convert to something that is ignored
by most synthesis tools.  I forget are you mainly
targeting Verilog or VHDL?

Regards,
Chris


~~~[Example]~~~
     def m_assert(clock, reset, inc, load, x, y):
         @always_seq(clock.posedge, reset=reset)
         def rtl():
             assert inc != load
             if inc:
                 y.next = y + 1
             elif load:
                 y.next = x
         return rtl


     clock = Signal(bool(0))
     reset = ResetSignal(0, active=0, async=True)
     inc,load = [Signal(bool(0)) for _ in range(2)]
     x,y = [Signal(intbv(0)[16:0]) for _ in range(2)]
     toVerilog(m_assert, clock, reset, inc, load, x, y)

~~~
     // snip of the converted verilog
     always @(posedge clock, negedge reset) begin: M_ASSERT_RTL
         if (reset == 0) begin
             y <= 0;
         end
         else begin
             if ((inc != load) !== 1) begin
                 $display("*** AssertionError ***");
             end
             if (inc) begin
                 y <= (y + 1);
             end
             else if (load) begin
                 y <= x;
             end
         end
     end