[myhdl-list] assert and synthesizable code

[Henry G. <he...@ca...>]

Not being terribly au fait with what is and is not synthesizable Verilog 
or VHDL, are python asserts converted into something that is 
synthesizable (or at least, will pass through the synthesis stage)?

Is the better way to put the assert in a `if __debug__:` clause if I 
don't want it synthesized?

Cheers,

Henry