[myhdl-list] Shadow signal

[Raman M. <rmu...@ho...>]

Hi All,

Thank you very much for MyHDL. We have been able to use it successfully for our projects.
I am facing one issue, and here my understanding is weak.The line of code that  creates a list of shadow signals from the input bus is not getting translated to verilog.I do not know what I am doing wrong or am missing. If you have any suggestion, it will be very helpful for me.
Below is the sample code:
from myhdl import *
def iso_pricing_check(                        ask_price_levels_i,                        price_o,
                        WIDTH=24,                        NUM_LEVELS=4                     ):

  # this line of code of slicing the signal and generating list of shadow signals is  # not getting translated into verilog.  ask_price_levels = [ask_price_levels_i((i+1)*WIDTH, i*WIDTH) for i in range(0, NUM_LEVELS)]
  @always_comb  def ask_price_logic():    # just giving the last level price as output    price_o = ask_price_levels[NUM_LEVELS-1]
  return instances()
def convert():    WIDTH = 24    NUM_LEVELS = 4
    ask_price_levels_i = Signal(intbv(0)[NUM_LEVELS*24:])    price_o = Signal(intbv(0)[WIDTH:])

    dut = toVerilog(    iso_pricing_check,                        ask_price_levels_i,                        price_o,
                        WIDTH=WIDTH,                        NUM_LEVELS=NUM_LEVELS,                     )
if __name__ == "__main__":  convert()

Thank you very much,Raman