Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?

[Christopher F. <chr...@gm...>]

On 1/23/2015 8:03 AM, Robert Peruzzi wrote:
> Jan,
>
> That clarifies the terminology.  Is there a way to read a variable in one
> circuit block from a different circuit block?
>

The answers have been yes but not in an OOMR
fashion.  I imagine you are looking for some
examples.  I am willing to provide some but
it will be many days before I can do so.

The topic being discusses is really Python
scope and Python scope accessibility.

I think it is worth considering if OOMR is the
correct approach.  I am sure the Python communities,
while working with whitebox/clearbox testings,
have discussed this type of access (i.e. easily
accessing internals).

A tweak on the approach Jan suggested would be
to create a global dict where you can drop the
signals you want to access:

     #project_globals.py file
     GlobalSignals = {}

     # design file 1
     from project_globals import GlobalSignals

     def model_subcircuit(*ports, name='subckt1'):
        sig1 = ...
        sig2 = ...

        GlobalSignals[name] = dict(sig1=sig1, sig2=seg2)

     # test file 1
     from project_globals import GlobalSignals

     def test():
         ...
         sig1 = GlobalSignals['subckt1']['sig1']

(note the above is example/pseudo code with many
shortcuts taken)

If you really prefer hierarchical access with "." vs
dictionary key names you can convert a dict to a
GlobalSignal class ...

The above is one option but has the downside of
limited scalability and some extra coding / maintenance
(e.g. providing a name).

Regards,
Chris

>
>
> From: ja...@ja... [mailto:ja...@ja...]
> Sent: Thursday, January 22, 2015 6:05 PM
> To: General discussions on MyHDL
> Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to
> Verilog's OOMR?
>
>
>
>
> I was talking about Python modules and importing them, e.g. to access Signal
> objects in them.
>
> Sent from Yahoo Mail on Android
> <https://overview.mail.yahoo.com/mobile/?.src=Android>
>
>
> From:"Robert Peruzzi" <bpe...@xt...
> <mailto:bpe...@xt...> >
> Date:Thu, Jan 22, 2015 at 22:16
> Subject:Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's
> OOMR?
>
> Jan,
> Thank you for your reply.  I don't want to confuse how I use the word
> module.  A circuit module, like an op-amp or A/D converter is also known as
> a circuit block.  Let me refer to it in this discussion as a circuit block.
> So we write a MyHDL model of an Op-Amp circuit block, and that model
> contains a module for its digital controls (like PowerDown) and separate
> modules for its bias, power supply and signal inputs?
> Bob P.
>
>
> -----Original Message-----
> From: Jan Decaluwe [mailto:ja...@ja... <javascript:return> ]
> Sent: Thursday, January 22, 2015 4:08 PM
> To: myh...@li... <javascript:return>
> Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to
> Verilog's OOMR?
>
> On 01/21/2015 11:45 PM, Robert Peruzzi wrote:
>
>> MyHDL is the tool of choice of my new client - for digital design and
>> verification.  My task is to use MyHDL for modeling analog and
>> mixed-signal blocks, and tie them into a full chip and its testbench.
>> To do so, I need to find the MyHDL equivalent of Verilog's "out of
>> module reference" (OOMR).  After a few hours searching, I have not
>> found it.
>
> Assuming the signals are special so that you can plan for them, you could
> put them in a separate module, and import that module wherever you need
> those signals.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
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