Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?

[Robert P. <bpe...@xt...>]

Chris,
Nice sine generator.  Similar approach to mine using Verilog.  Is there a
way to conduct that signal into a discrete-time analog processing block that
for example, multiplies its input by two?  In Verilog-AMS, in
continuous-time analog that would be 
	V(Vout) <+ 2.0 * V(Vin);

In Verilog, in discrete-time analog using OOMR, that would be something like
	assign ASCLK = TOP.SG.ASCLK_OOMR;
               always @(posedge ASCLK) begin
                   VIN_OOMR = TOP.SG.VSIG_OOMR;
                   Vout = 2.0 * VIN_OOMR;
               end	

-----Original Message-----
From: Christopher Felton [mailto:chr...@gm...] 
Sent: Thursday, January 22, 2015 11:40 AM
To: myh...@li...
Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to
Verilog's OOMR?

On 1/21/2015 4:45 PM, Robert Peruzzi wrote:
> Today I heard the word "MyHDL" for the first time!
<snip>
>  Verilog, unlike VHDL, has no concept of real ports or wires, so I 
> write the module receiving the analog signal to look inside the source
module via OOMR.
>

Note, if you are modeling in Python/MyHDL there are no limitations on the
ports.  The OOMR type approach is probably not what you want in this case.
This is a very important point, if you are modeling you have lot of
flexibility!

I put together a simple example:
http://nbviewer.ipython.org/github/cfelton/musicbox_simple/blob/master/analo
g_model.ipynb

If you use object for all your models you can access all the object
attributes just like OOMR.

Regards,
Chris





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