Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?

[Robert P. <bpe...@xt...>]

Chris, Uri, anyone else interested,

 

Here is what I do in plain Verilog to transport an analog signal from block
to block;

 

Hierarchical path from top level to the signal generator:

               TOP.SG

Real variable VSIG_OOMR is the stimulus signal.  The module has an INOUT
port named VSIG which in this model is used for hand-shaking with the signal
receiver.

The signal generator also creates an analog sample clock

reg ASCLK_OOMR;

There is no ASCLK_OOMR port or wire. It is a fictitious clock, and is
accessed via OOMR from the signal receiver.

 


Hierarchical path from top level to the signal receiver:

               TOP.AFE

The AFE module has an INOUT port named VIN which in this module is used for
hand-shaking with the signal generator.

The AFE module has a real variable VIN_OOMR which is gets its analog input
using this snippet of code

               assign ASCLK = TOP.SG.ASCLK_OOMR;

               .

               always @(posedge ASCLK) begin

                   VIN_OOMR = TOP.SIG.VSIG_OOMR;

               .

               end

               .

 

Within the AFE module, discrete-time analog signal processing is done at the
ASCLK rate on VIN_OOMR

 

Now, is there an equivalent to this in MyHDL?  I believe I can do
discrete-time analog signal processing on real variables within a MyHDL
model.  Correct?

 

The question is, can I grab a real or logic variable value from a different
MyHDL instantiation?

Thanks!

Bob P.

 

 

 

 

-----Original Message-----
From: Christopher Felton [mailto:chr...@gm...] 
Sent: Wednesday, January 21, 2015 7:53 PM
To: myh...@li...
Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to
Verilog's OOMR?

 

On 1/21/2015 4:45 PM, Robert Peruzzi wrote:

> Today I heard the word "MyHDL" for the first time!

<snip>

> 

> Is there something in MyHDL equivalent to OOMR?  What is it called?

 

The short answer is no.

 

But I am not sure I exactly follow what you want to do.  Do you want to
access signals/variables in the Python/MyHDL environment?  Or do you want to
dig down into the Verilog simulation from Python/MyHDL (cosimulation)?

 

If it is the first, there might be a simple utility function you can build
to do what you want.

 

If it is that later, no tool exists to support this.

You can manually export (import?) each signal to the Python environment.

 

Regards,

Chris Felton

 

 

 

 

 

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