Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?
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Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?
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From: Christopher F. <chr...@gm...> - 2015-01-22 16:40:26
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On 1/21/2015 4:45 PM, Robert Peruzzi wrote: > Today I heard the word "MyHDL" for the first time! <snip> > Verilog, unlike VHDL, has no concept of real ports or wires, so I write the module > receiving the analog signal to look inside the source module via OOMR. > Note, if you are modeling in Python/MyHDL there are no limitations on the ports. The OOMR type approach is probably not what you want in this case. This is a very important point, if you are modeling you have lot of flexibility! I put together a simple example: http://nbviewer.ipython.org/github/cfelton/musicbox_simple/blob/master/analog_model.ipynb If you use object for all your models you can access all the object attributes just like OOMR. Regards, Chris |
