Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?

[Robert P. <bpe...@xt...>]

Thank you, Uri.  This isn’t exactly what I’m doing, but it may hold clues to a solution.

Bob P.

 

 

From: Uri Nix [mailto:ur...@gm...] 
Sent: Thursday, January 22, 2015 9:52 AM
To: General discussions on MyHDL
Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?

 

Hi Robert,

 

Might be relevant: http://old.myhdl.org/doku.php/projects:mixedmodesimulation

 

Cheers,

Uri

 

On 22 January 2015 at 00:45, Robert Peruzzi <bpe...@xt... <mailto:bpe...@xt...> > wrote:

Today I heard the word “MyHDL” for the first time!  

 

MyHDL is the tool of choice of my new client – for digital design and verification.  My task is to use MyHDL for modeling analog and mixed-signal blocks, and tie them into a full chip and its testbench.  To do so, I need to find the MyHDL equivalent of Verilog’s “out of module reference” (OOMR).  After a few hours searching, I have not found it.  I hope you will take the time to help. Here’s a quick explanation.

 

Modeling a signal flow of voltages or currents is sufficient for high-level verification, as opposed to modeling physically conservative networks obeying Kirchhoff’s laws.  Many times I use ordinary Verilog for models and Icarus for simulations.  An analog “source” model for analog signals uses a fictitious sampling clock with impossibly high sampling rate to create a sequence of real values on a real variable inside that model.  Verilog, unlike VHDL, has no concept of real ports or wires, so I write the module receiving the analog signal to look inside the source module via OOMR.  

 

Using this OOMR approach, the analog signal flows from a source through, say, an amplifier, then a filter, to an analog-to-digital converter.  The ports and wires of the netlist cannot conduct the analog signal so they may be separately used for verifying continuity.

 

Is there something in MyHDL equivalent to OOMR?  What is it called?  

 

Thank you very much.

 

Robert Peruzzi

Principal Engineer

XtremeEDA

Direct: +1 610 462 3939 <tel:%2B1%20610%20462%203939> 

BPe...@Xt... <mailto:BPe...@Xt...> 

 

 


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