Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?

[Christopher F. <chr...@gm...>]

On 1/21/2015 4:45 PM, Robert Peruzzi wrote:
> Today I heard the word "MyHDL" for the first time!
<snip>
>
> Is there something in MyHDL equivalent to OOMR?  What is it called?

The short answer is no.

But I am not sure I exactly follow what you want
to do.  Do you want to access signals/variables in
the Python/MyHDL environment?  Or do you want to
dig down into the Verilog simulation from
Python/MyHDL (cosimulation)?

If it is the first, there might be a simple utility
function you can build to do what you want.

If it is that later, no tool exists to support this.
You can manually export (import?) each signal to
the Python environment.

Regards,
Chris Felton