Re: [myhdl-list] reusable blocks with different interfaces

[Josy B. <jos...@gm...>]

Keerthan JC <jckeerthan <at> gmail.com> writes:

> 
> VHDL records are not isomorphic to python objects or SV interfaces. A
> VHDL record is similar to a SV struct.
> There is no general way to convert MyHDL interfaces to VHDL records.
> The way conversion currently works, you can think of attribute
> references as pointers to Signals rather than Interface objects being
> special datatypes.
> 
> wrt qsys, I don't understand how records simplify qsys components.
> Could you share some example code with me?
> <snip>

I'm *not* looking to convert MyHDL interfaces into VHDL records. You keep 
hanging on to that idea, but I never said so. My original question was:
Say we have used an interface in MyHDL to model a structured type in a 
module. The module will have to be usable both for import in other MyHDL 
modules, but also as a standalone component in Qsys. The interface works 
fine inside MyHDL. But we need to flatten this interface to a 
std_logic_vector for Qsys. Similar what a I do when using VHDL records: I 
write to_std_logic_vector( record_type_x r) and to_record_type_x( 
std_logic_vector v) functions. That was essentially my question in my first 
follow-up in this thread. I repeat it here:
<quote>
It would be nice if we also had a 'magic' way to export / import the 
interfaces as a std_logic_vector. As this is what Altera's Qsys 
understand. I doubt that Xilinx' IP Integrator will be any smarter.
</quote>
Perhaps I should have specified that it was about the *data* signal proper, 
not the global Sink or Source.
I have written several dozen Qsys components in VHDL and MyHDL and have 
done a mid-size MyHDL project using a Support Vector Machine (6700 lines of 
generated VHDL).

I'll post code on Github, later ...

Best regards,

Josy