Re: [myhdl-list] reusable blocks with different interfaces

[Josy B. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:
> <snip> 
> First we need to define (review) the purpose of the
> generated Verilog and VHDL.  Is it a convenient
> intermediate representation or is MyHDL intended to be
> a V* generator (i.e. is the generated V* modified by
> the user - bootstrap)?
> 
> The V* are convenient IRs [1] and although MyHDL has
> readable converted code (etc.), the converted V* are
> akin to an IR more than a usable standalone piece of
> code (e.g. parameters are not preserved).
> 
> But, in my opinion, interoperability is important and in
> this case I think it is better supported by tools/plugins
> than conversion support.  As  <at> jck mentioned there are
> some processes (naming conventions) that can be used.  If
> I get time in the near future I will try and but together
> an example using  <at> jck suggestion.
> 
> Regards,
> Chris
> (as usual my 2 cents with normal disclaimers :)
> 
> [1] Things change over time and I see to have many false memories,
>      best of my knowledge this is Jan's goal/vision with V*.
> 
> <snip>
You are right, I too see the generated V* as just a convenient 
intermediate representation. This is exactly my point of 'converting' 
MyHDL interfaces into std_logic_vectors (and back) for use in other 
tools. Same reason I am currently (after hours ...) writing a Python 
utility to generate the necessary supporting files, so we can almost 
forget the IR completely and treat is an an opaque something (a black 
box). My utility does away with those (ugly) (Altera) naming conventions 
as it works with ST- and MM- interfaces directly. I hope I can post some 
debugged code soon now. I have an example module working for ST-
interfaces and am now working on an example that also has a MM-Slave 
interface. 
I haven't used interfaces to model Avalon ST-interfaces, yet. We looked 
into them for a project and tried to enhanced this further, but stumbled 
a few times, so I decide to write the project (as it was a fixed-price 
offer from our side) using the 'standard' interconnection method. 
Now an ST-module with MyHDL interfaces may/will conflict with my 
utility, but I'll learn ...

Best regards,

Josy