Re: [myhdl-list] reusable blocks with different interfaces

[Christopher F. <chr...@gm...>]

On 1/19/2015 3:23 PM, Josy Boelen wrote:
> Christopher Felton <chris.felton <at> gmail.com> writes:
>> <snip>
>>> Henry is talking about extending the interfaces concept of MyHDL.
> When
>>> converted to VHDL this would result in having structured types (e.g.
> a
>>> record) as ports.
>>
>> I don't think supporting conversion to VHDL records
>> would be a good idea.  Then the Verilog and VHDL
>> conversions would diverge.
>>
>> I don't believe I understand the use case?  Is this
>> intended to simplify wiring up modules (components)
>> after conversion?
<snip>
> Keeping VHDL on a leash to please Verilog is, IMHO, hampering MyHDL's
> progress and adoption. Maybe it is time to start a to_SystemVerilog() at
> the same time expanding to_VHDL()?
>

First we need to define (review) the purpose of the
generated Verilog and VHDL.  Is it a convenient
intermediate representation or is MyHDL intended to be
a V* generator (i.e. is the generated V* modified by
the user - bootstrap)?

The V* are convenient IRs [1] and although MyHDL has
readable converted code (etc.), the converted V* are
akin to an IR more than a usable standalone piece of
code (e.g. parameters are not preserved).

But, in my opinion, interoperability is important and in
this case I think it is better supported by tools/plugins
than conversion support.  As @jck mentioned there are
some processes (naming conventions) that can be used.  If
I get time in the near future I will try and but together
an example using @jck suggestion.

Regards,
Chris
(as usual my 2 cents with normal disclaimers :)

[1] Things change over time and I see to have many false memories,
     best of my knowledge this is Jan's goal/vision with V*.