Re: [myhdl-list] reusable blocks with different interfaces

[Josy B. <jos...@gm...>]

Henry Gomersall <heng <at> cantab.net> writes:

> 
> On 19/01/15 21:23, Josy Boelen wrote:
> > Keeping VHDL on a leash to please Verilog is, IMHO, hampering MyHDL's
> > progress and adoption. Maybe it is time to start a to_SystemVerilog() at
> > the same time expanding to_VHDL()?
> 
> Given Python is a fully featured language, it would be perfectly 
> possible to write _anything_ into VHDL/Verilog, it's just developer time 
> to make this possible. The correct way IMO is to do the translation in 
> python and not try to match the features of some intermediate language 
> at all. Still, targetting VHDL and Verilog is very sensible.
> 
> Henry
> 

I'm a VHDL-guy (wouldn't touch Verilog with a bargepole).
VHDL has a few extras Verilog doesn't have, aside from Verilog's ugly 
blocking and non-blocking'. 
A practical example: Once there was this site 'All Programmable Planet'. A 
blog/thread was about the 'Game Of Life'. Out of curiosity I coded a VHDL 
version of it. I used, of course, a (true) 2D array to represent the cells. 
I later re-coded this in MyHDL and as MyHDL suffers from Verilogitis (I 
deliberately make it sound like a disease) I had to recode it into a 1D 
array, otherwise it would not convert. 

Now I couldn't care less that how the converted (VHDL or even Verilog) code 
looks, as long as it works but it is a not a step forward to 'advance by 
using Python, but limit yourself to Verilog-able constructs'.
So in my (not so humble anymore) opinion there is a brighter future for 
MyHDL, if only we manage to lift it above the Verilog coding rules. 

Regards,

Josy