Re: [myhdl-list] reusable blocks with different interfaces

[Henry G. <he...@ca...>]

On 19/01/15 21:23, Josy Boelen wrote:
> Keeping VHDL on a leash to please Verilog is, IMHO, hampering MyHDL's
> progress and adoption. Maybe it is time to start a to_SystemVerilog() at
> the same time expanding to_VHDL()?

Given Python is a fully featured language, it would be perfectly 
possible to write _anything_ into VHDL/Verilog, it's just developer time 
to make this possible. The correct way IMO is to do the translation in 
python and not try to match the features of some intermediate language 
at all. Still, targetting VHDL and Verilog is very sensible.

Henry