Re: [myhdl-list] reusable blocks with different interfaces

[Josy B. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:

> 
> <snip>
> > Henry is talking about extending the interfaces concept of MyHDL. 
When
> > converted to VHDL this would result in having structured types (e.g. 
a
> > record) as ports.
> 
> I don't think supporting conversion to VHDL records
> would be a good idea.  Then the Verilog and VHDL
> conversions would diverge.
> 
> I don't believe I understand the use case?  Is this
> intended to simplify wiring up modules (components)
> after conversion?
> 
> Regards,
> Chris
> <snip>

Apparently I have a problem explaining things (and may now mess it up 
even more):

If we elaborate on the interfaces concept, we can have interfaces (which 
I see as kind of records in records) nicely connecting up in MyHDL. 
Eventually we have to convert into VHDL and integrate it in our top 
level project. Now, in the Altera-world some we have Qsys to make live 
easy. Except that Qsys only understands std_logic and std_logic_vector. 
Say we now define an interface in MyHDL to represent a structured type 
we have to write a to_std_logic_vector() and a to_myinterface() (as I 
now do in VHDL whenever a define a record)  function to 'map' the one to 
the other and back. My expectation is that this could be handled 
automagically. This would save us from writing those 'wrapper modules' 
to use MyHDL originated modules with 'interfaces' in order to use them 
with Qsys (or Xilinx' IP Integrator?).

Keeping VHDL on a leash to please Verilog is, IMHO, hampering MyHDL's 
progress and adoption. Maybe it is time to start a to_SystemVerilog() at 
the same time expanding to_VHDL()?

Best regards,

Josy



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