Re: [myhdl-list] reusable blocks with different interfaces

[Christopher F. <chr...@gm...>]

<snip>
> Henry is talking about extending the interfaces concept of MyHDL. When
> converted to VHDL this would result in having structured types (e.g. a
> record) as ports.

I don't think supporting conversion to VHDL records
would be a good idea.  Then the Verilog and VHDL
conversions would diverge.

I don't believe I understand the use case?  Is this
intended to simplify wiring up modules (components)
after conversion?

Regards,
Chris